Tensor Compiler & Domain-Specific Language for ML Frameworks
[PlaidML v1 Repository]
Contributed to PlaidML, an MLIR-based tensor compiler targeting heterogeneous hardware (NVIDIA, AMD, Intel GPUs/CPUs, Metal). Developed and extended the Tile eDSL (C++/Python) to express tensor computations and integrate with ONNX Runtime, OpenVINO, and TensorFlow.
Key contributions:
- Designed and implemented the PlaidML execution provider for ONNX Runtime, extending Tile to support ONNX operator lowering and backend execution.
- Developed abstractions in Tile to express stencil-based and reduction-heavy scientific workloads within a tensor compiler infrastructure.
- Collaborated with University of Washington and Intel Labs to implement grid-based volume and surface integral formulations in Tile, enabling structured stencil + reduction kernels to execute on accelerator backends.
- Worked with AI acceleration hardware teams on hardware–software co-design, analyzing memory access patterns and backend execution efficiency.
Example workload: SciTile implementation of grid-based surface and volume integrals , based on the formulation in “Treat All Integrals as Volume Integrals” .
Face Recognition Module for Intelligent PC Platform
Images © Intel Corporation. Source: Intel COMPUTEX 2019 Press Materials
Developed a face-recognition module for Intel's ambient computing concept platform, demonstrated at COMPUTEX 2019. The system used a 360° camera to identify users and dynamically adjust the device interface: when closed, recognized users were presented with contextual information on an auxiliary touchbar display; when opened, the system authenticated and logged users into the primary OS.
Implementation involved cross-OS communication, real-time inference integration, and synchronization between device drivers, camera pipelines, and UI subsystems—requiring performance-sensitive, reliability-critical software design for a dual-OS shared peripheral architecture.